Computation and Language

Analyse de systèmes temps-réels de sûreté et mitigation de leurs interférences temporelles

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Authors: Jean Guyomarc'H

Safety-critical real-time systems often rely on time provisioning strategies. These are especially a standard practice in avionics. They consist in assigning quotas of time to the tasks that compose the system, such that each task is allotted with a sufficient amount of execution time to complete while respecting strict latency and pacing constraints. WCET (Worst-Case Execution Times) are frequently used as the foundation of this temporal partitioning. WCET estimation is therefore a crucial step in the development of safety-critical real-time systems. Their values must be sound to guarantee the nominal execution of the system, but they also must be tight, so the system can benefit from a satisfactory equilibrium between safety and efficiency. A major obstacle to WCET evaluation resides in the occurrence of timing interferences at run-time. They are caused by contemporary off-the-shelf architectures that rely on statistically efficient hardware features (for example, the caches), that greatly reduce average execution times, but degrade some timing properties of interest, which is detrimental to the characterization of real-time systems. As a result, WCET are often greatly overestimated, affecting temporal partitioning. The work presented in this thesis seek to analyze specific safety-critical real-time systems to mitigate the timing interferences they are the most sensitive with. The increasing use of multi-core platforms leads to new classes of timing interferences: simultaneous accesses to shared hardware resources. This work aims at preventing them by design, effectively avoiding their occurrence at run-time. Hardware caches are also a well-known source of timing interferences. The second part of this thesis is dedicated to analyzing compiled programs to characterize the wholeness of their memory accesses. The end goal of this technique is to propose memory partitioning strategies allowing a better use of caches that encompasses the worst cases.