FPGA accelerators HLS-based design of hyper complex LMS filters

In this paper, it is explored the use of the high- level synthesis (HLS) tool to design field-programmable gate array (FPGA)-based Quaternion Least Mean Square (QLMS) filters. The QLMS behaviour is modelled in system level C-code, and performance criteria, such as parallelism level and timing closure requirements, set through specific directives. The design outcome is a synthesizable hardware description model of the QLMS filter, and its implementation performance is evaluated for different data type representations. The results demonstrate that HLS is a framework that allows rapid design development and efficient FPGA implementation and opens the hyper complex filters hardware design to a larger design community.