Ageing of SiC JFET transistors under repetitive current limitation conditions

In power applications using normally on transistors, short circuit or current limitation modes can be recurrent during operation, especially when powering converters. So, studying the robustness of these devices under such severe condition is an important issue. The paper presents ageing tests of normally on SiC JFET prototype transistors from SiCED subjected to repetitive short circuit operations. Experimental tests are detailed and the evolution of electrical parameters during ageing is presented. Especially, the evolution during tests of ageing indicators like on-state resistance and saturation current is presented. Numerical investigations have been performed in order to estimate temperature during short circuit operation and to quantify the effect of the maximum temperature on the ageing process