Analyse de matériaux pour la modélisation des mécanismes de défaillance dans les modules électroniques de puissance

This PhD focuses on the study of the lifetime of components and power semiconductor modules under thermal constraints, when power devices are used at high temperature or under high temperature cycles. The areas covered by this study relate more particularly to extremely harsh applications such as aerospace constraints. A power device is an assembly of different materials (semiconductors, solders, ceramics, conductors) with mechanical properties, including coefficient of thermal expansion (CTE). Losses in the die and ambient temperature variations (mission pro les) are responsible for strain constraints at material interfaces due to CTE mismatch between the different materials. Failure modes result for mechanical constraints so study was done in collaboration between LMT and SATIE laboratories (Farman Institute). The mechanical study completed experimental characterizations and accelerated aging of power semiconductor modules. These studies involved the development of specific aging tests allowing thermal cycles (thermal air streamer to force the power assemblies under thermal cycles of high amplitude) and active power cycles (use of hard working conditions such as short circuit for accelerating the aging of parts of the assembly).The first part of this manuscript presents the physical principles set in. We briefly introduce the concepts of fracture mechanics and the physical couplings.The second part focuses on the fractured DCB ceramic substrates. This failure can arise from defects randomly distributed in the material. We consider the problem using a statistical approach where we introduce the "weak link theory". The other cause of failure is the presence of geometrical defects called singularity where there is stress concentration requiring a deterministic approach. On this occasion we introduce the stress intensity factor which allows to study the failure problems associated with singular zone.The last part will focus on the aging of the transistor metallization. The search for indicators of aging has requested the development of several electrical characterization test benches for the precise measurement of different electrical parameters (leakage currents, threshold voltages, voltage drop in the on state ...) in a controlled thermal environment. Moreover, these electrical characterizations are correlated with observations at different aging states of the metallization degradation using a scanning electron microscope. We seek to show how the change in the morphology of the metallization can change the electrical characteristics of tested power transistors.