Technique et Méthodologie de Conception du Réseau de Distribution d'Alimentation d'une Carte Electronique Rapide à Haute Densité d'Interconnexion

Today's economical context leads electronics and high-tech corporations not only to innovate with a sustained rhythm but also to reduce the design cycle of new products. In order to remain competitive, these corporations must release regularly new products with new functionalities or enhancing performances of the last generation of this product. The enhancement from one generation of the product to the other can be quantified by the speed of execution of a task, the package size or form factor, the battery life and power consumption.The design methodology following these constraints is thus very tough. Indeed, integration of new functionalities as miniaturization of products imply a densification of the printed circuit board. The number of layer in the stack up is increased, isolation between nets is reduced, the use of integrated circuits embedding different functions as SOC or SIP implies a multiplication of the number of voltages. Moreover the increase of circuit performances implies a increasing data rate exchanged between component of the same printed circuit board and occasioning a widening of the reference clock and signal frequency spectrum. These design constraints are the root cause of the apparition of electromagnetic compatibility, signal integrity and power integrity issues. Failure risks must then be limited by fully understanding phenomenon occurring on the board by, on one side, realizing a precise dimensioning pre layout analysis aiming the elimination or reduction of the issues at the beginning of the design cycle, and on the other side, validating the layout by post layout simulation once the printed circuit board routed.This study proposed by Thales Communication and Security in collaboration with public research laboratory SATIE (System and Application of Energy and Information Technologies) of Ecole Normale Supérieure de Cachan within a industrial convention for development through research aims to develop a design methodology for power delivery network of digital printed circuit board with the goal of ensuring good behavior without or by reducing the number of prototypes.The first chapter of this manuscript include an introduction to the context of the study, a precise description of the studied system and the physical phenomenon ruling its behavior, and finally a state of the art of the power integrity technique analysis. A presentation of the test vehicle, designed during the work and support of all measurement results will constitute the focus of second chapter. This chapter presents and describes all the scenarios and implementations created for the observation and measurement of Power Integrity phenomenon and realise measurement-simulation results correlation. In a third part, modeling techniques of each element of the Power Delivery Network are described. The validity of the models is proven by correlating simulation results of each element with measurement results. The fourth chapter presents the analysis and design methodology developed from the results of the different modeling techniques presented in the previous chapter. Simulation tools and their configuration are precisely described and simulation results are compared with measurement results obtained on the test vehicle for the whole system. In the fifth chapter, the interest of power delivery network model will be extended to signal integrity analysis demonstrating how including this model allows to obtain simulation results closer from measurement results by running Signal Integrity Power aware simulation. Finally, the last part of this document synthetizes the work realized and presented in this document, takes a critical look on it and proposes future works and orientations to extend knowledges and understanding of Power Integrity Phenomenon.