Modeling SiC MOSFETs threshold voltage drift : Constant and varying gate voltage stress conditions

This work presents a comprehensive methodology for modeling the threshold voltage drift of SiC MOSFETs based on experimental gate switching stress data taken from the literature. The proposed approach enables the evaluation of cumulative degradation under successive or combined electrical stresses. The developed model provides deep insight into the underlying aging mechanisms and allows the prediction of parameter shifts under realistic converter operation conditions. Furthermore, integrating the proposed drift model into a circuit-level simulation environment could facilitate the prediction of threshold voltage evolution in parallel SiC MOSFET configurations, which are common in high-power applications. Such integration supports the development of predictive maintenance strategies and reliability-oriented design frameworks for next-generation SiC-based power converters. The proposed methodology thus contributes to improving both the reliability modeling accuracy and the lifecycle gate switching stress performance assessment of advanced power electronic systems.