Failure modes and robustness of SiC JFET transistors under current limiting operations

The paper presents results of ageing tests of normally-on SiC JFET prototype transistors from SiCED subjected to repetitive short circuit modes corresponding to current limitation operations. Experimental tests are detailed and the evolution during tests of ageing indicators like on-state resistance and saturation current are discussed. Finally, thermal simulation results are presented in order to understand and explain evolutions of some ageing indicators.