Etude de la robustesse de transistors JFET à base de SiC vis-à-vis de stress électriques

The work presented in this thesis was conducted between SATIE and LTN IFSTTAR laboratories. It focuses on the study of the robustness of SiC power components subjected to hard working conditions for high switching frequency, high power density and high temperature applications. The work also presents a study on the robustness of a dedicated package adapted to high temperature applications. The robustness of several SiC VJFETs from a particular manufacturer (SemiSouth) was studied in avalanche and short circuit modes in order to estimate the energies that can withstand these components in these operating modes. The experimental protocol also includes thermal models to quantify the crystal temperature and to highlight the ageing physical mechanisms causing failure. Therefore, we had developed a finite element model to estimate the thermal junction temperature of the SiC JFET in extreme working conditions to try to relate the failure to the maximum temperature reached after each cycle. Finally, we described the physical mechanisms behind the degradations that explain ultimately the destruction of ageing transistors under repetitive avalanche mode. A ceramic substrate made of Si3N4 has been the support of studies conducted in this thesis on the packaging reliability. We characterized the degradation of these substrates by acoustic analysis after ageing by thermal cycling of high amplitude. A thermo-mechanical model was developed to estimate the mechanical stresses in the assembly and validate the experimental results. Finally, we have initiated thermal diagnostic studies on SiC JFET chips. We have shown that thermal impedance measurements can be used for the detection of delamination defects in a power assembly.