Étude de la robustesse de transistors GaN en régime de court-circuit

This thesis aims to evaluate the short-circuit robustness of commercial GaN 600 V normally-off transistors. A review of the literature describes the different structures of GaN transistors, their possible applications, and study the short-circuit tests carried out from 2013 to 2021. The robustness of the transistors is evaluated by measuring the Time Leading to failure (TLF). For 600/650 V transistors, when the DC bus voltage is set to 400 V, the TLF is less than 10 µs. For lower DC bus voltages (below 300/350 V), rapid failures are also recorded (TLF100 µs).Three short-circuit benches were manufactured, with low parasitic inductance to avoid self-sustaining oscillations.Four HEMT structures were tested: two P-GaN HEMTs (from GaN Systems and Panasonic manufacturers), a cascode component (from the Transphorm manufacturer) and a MIS-HEMT, prototype of the CEA-LETI. Between 2016 and 2019, more than 200 destructive short-circuit tests were carried out. The robustness is on average low, and very dispersed. The bus voltage strongly impacts the TLF. The robustness has improved batch after batch for the P-GaN gate HEMTs of GaN Systems. On the other hand, the cascode transistor (Transphorm) and the HEMT GIT (Panasonic) are fragile when the DC bus voltage is set to 400 V.Finally, around fifteen P-GaN gate HEMTs were characterized before subjecting them to a destructive short-circuit test, and no correlation was found between the TLF observed and any of the parameters measured during these characterizations.